9789048195909-904819590X-VLSI Physical Design: From Graph Partitioning to Timing Closure

VLSI Physical Design: From Graph Partitioning to Timing Closure

ISBN-13: 9789048195909
ISBN-10: 904819590X
Edition: 1
Author: Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu
Publication date: 2011
Publisher: Springer
Format: Hardcover 321 pages
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Book details

ISBN-13: 9789048195909
ISBN-10: 904819590X
Edition: 1
Author: Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu
Publication date: 2011
Publisher: Springer
Format: Hardcover 321 pages

Summary

VLSI Physical Design: From Graph Partitioning to Timing Closure (ISBN-13: 9789048195909 and ISBN-10: 904819590X), written by authors Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu, was published by Springer in 2011. With an overall rating of 3.5 stars, it's a notable title among other Drafting & Presentation (Architecture) books. You can easily purchase or rent VLSI Physical Design: From Graph Partitioning to Timing Closure (Hardcover) from BooksRun, along with many other new and used Drafting & Presentation books and textbooks. And, if you're looking to sell your copy, our current buyback offer is $1.

Description

Design and optimization of integrated circuits are essential to the creation of new semiconductor chips, and physical optimizations are becoming more prominent as a result of semiconductor scaling. Modern chip design has become so complex that it is largely performed by specialized software, which is frequently updated to address advances in semiconductor technologies and increased problem complexities. A user of such software needs a high-level understanding of the underlying mathematical models and algorithms. On the other hand, a developer of such software must have a keen understanding of computer science aspects, including algorithmic performance bottlenecks and how various algorithms operate and interact.

"VLSI Physical Design: From Graph Partitioning to Timing Closure"

introduces and compares algorithms that are used during the physical design phase of integrated-circuit design, wherein a geometric chip layout is produced starting from an abstract circuit design. The emphasis is on essential and fundamental techniques, ranging from hypergraph partitioning and circuit placement to timing closure.


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