RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design

3.5
ISBN-13: 9781546776345
ISBN-10: 1546776346
Edition: 1
Author: Stuart Sutherland
Publication date: 2017
Publisher: CreateSpace Independent Publishing Platform
Format: Paperback 488 pages
Category: Design
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Book details

ISBN-13: 9781546776345
ISBN-10: 1546776346
Edition: 1
Author: Stuart Sutherland
Publication date: 2017
Publisher: CreateSpace Independent Publishing Platform
Format: Paperback 488 pages
Category: Design

Summary

Acknowledged authors Stuart Sutherland wrote RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design comprising 488 pages back in 2017. Textbook and eTextbook are published under ISBN 1546776346 and 9781546776345. Since then RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design textbook received total rating of 3.5 stars and was available to sell back to BooksRun online for the top buyback price of $ 31.58 or rent at the marketplace.

Description

This book is both a tutorial and a reference for engineers who use the SystemVerilog Hardware Description Language (HDL) to design ASICs and FPGAs. The book shows how to write SystemVerilog models at the Register Transfer Level (RTL) that simulate and synthesize correctly, with a focus on proper coding styles and best practices. SystemVerilog is the latest generation of the original Verilog language, and adds many important capabilities to efficiently and more accurately model increasingly complex designs. This book reflects the SystemVerilog-2012/2017 standards. This book is for engineers who already know, or who are learning, digital design engineering. The book does not present digital design theory; it shows how to apply that theory to write RTL models that simulate and synthesize correctly. The creator of the original Verilog Language, Phil Moorby says about this book (an excerpt from the book's Foreword): “Many published textbooks on the design side of SystemVerilog assume that the reader is familiar with Verilog, and simply explain the new extensions. It is time to leave behind the stepping-stones and to teach a single consistent and concise language in a single book, and maybe not even refer to the old ways at all! If you are a designer of digital systems, or a verification engineer searching for bugs in these designs, then SystemVerilog will provide you with significant benefits, and this book is a great place to learn the design aspects of SystemVerilog.”

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